16 jobs for "Design Verification Engineer"

Wireless SoC Design Verification Engineer

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Posted on Oct 16

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SCADA Commissioning Engineer

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Ingenieur Application departement Marin Cummins Saint - Herblain

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Lead Engineer - Thermal-Hydraulic Methods Development

At GE Vernova - Remote / Flexible

Posted on Oct 23

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Senior Software Engineer, Backend (Identity Data)

At Affirm - Remote / Flexible

Posted on Oct 20

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Senior Software Engineer, Backend (Identity Data)

At Affirm - Remote / Flexible

Posted on Oct 20

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Senior Test Lead

At Leidos - Remote / Flexible

Posted on Nov 5

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Engineer - Thermal-Hydraulic Methods Development

At GE Vernova - Remote / Flexible

Posted on Oct 23

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Lead Engineer - Reactor Nuclear Physics & Methods

At GE Vernova - Remote / Flexible

Posted on Oct 23

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Apple

Wireless SoC Design Verification Engineer

Remote / FlexiblePosted 23 days ago

Apply on company site View full job

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible various aspects of wireless silicon development with a particular emphasis on highly energy efficient design new technologies that impact the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

Preferred Qualifications
Experience with MAC or PHY Verification - a plus

Minimum Qualifications
BSc or MSC in Electrical Engineering or Computer Engineering
5+ years of verification experience
Solid verification skills in problem solving, constrained random testing, and debugging
Advanced knowledge of SystemVerilog and DV methodologies
Self-motivated and dedicated with proven creative thinking capabilities
Ability to handle multiple tasks and prioritise work to meet deadlines

About Apple

Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.

Size: 10,000+ employees
Industry: Technology

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