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Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, resourceful people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Join the team that optimizes and delivers world-class GPUs into Apple Silicon. As part of the GPU FE Implementation team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.

Description

The successful candidate will work closely with the RTL and PD (physical design) teams and be responsible for synthesis, analysis, and optimization of the delivered IP. For this role, use and develop advanced techniques spanning RTL/Synthesis/PNR to meet challenging timing, power and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Through this collaboration, you will deliver the best-in-class GPU's for the best consumer products. If you're ready to help chart the future of Apple Silicon, we'd love to talk to you.

Preferred Qualifications

Collaboration with Physical Design and Timing Analysis teams on physical concepts (floor-planning, placement, congestion, and timing constraints)

Demonstrated ability to solve complex problems across multiple technical domains

Ability to analyze architectural critical paths and drive multi-block closure across RTL Design and Physical Design teams

Develop and Drive adoption of innovative methodologies across projects and teams

Familiarity with DFT insertion

Familiarity with simulation, debugging tools and experience of working closely with design verification team

Experience working on GPUs/CPUs is desirable

Minimum Qualifications

Experience driving block level synthesis and optimizations

Experience with RTL design improvement for optimal Area, Timing Power

Experience debugging complex logic equivalence issues and in netlist checks to validate functionality and netlist quality

Experience implementing ECOs for functionality and timing

Experience with one or more of: reset domain, multi-clock domain, multi-power domain (UPF), linting tools across RTL and Gate-Level

Scripting experience in ASIC flows - python, tcl, Perl, Data manipulation

BS + 10 years of relevant experience

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

About Apple

Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.

Size: 10,000+ employees
Industry: Technology

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