715 jobs for "AI Engineer 5"

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At Cadence - Hyderabad

Posted on Aug 9

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Posted on Aug 3

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Machine Learning Engineer Intern (Global E-Commerce, Risk Control) - 2027 Start

Posted on Aug 3

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Machine Learning Engineer Graduate (Global E-Commerce, Risk Control) - 2027 Start (PhD)

Posted on Aug 3

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Machine Learning Engineer Graduate (Global E-Commerce, Risk Control) - 2027 Start

Posted on Aug 3

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Application Engineer - IV

At Vanguard - Hyderabad

Posted on Jun 13

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Senior Design Engineer (Founding Engineer) - TikTok

At TikTok - San Jose

Posted on Jun 5

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Application Engineer (ETCH)

At Applied Materials - Hwaseong-Castle

Posted on May 27

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Lead EDA Software Engineer (C++, Characterization)

At Cadence - San Jose

Posted on May 7

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Research Engineer - Ads Integrity

At TikTok - San Jose

Posted on Apr 2

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At TikTok - San Jose

Posted on Nov 1

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Machine Learning Engineer , E-commerce Merchant Growth (LLM & Agentic Systems)

Posted on Oct 28

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Machine Learning Engineer, TikTok Core Feed Recommendation - Dedup

At TikTok - San Jose

Posted on May 29

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Senior Machine Learning Engineer, TikTok Core Feed Recommendation - Dedup

At TikTok - San Jose

Posted on May 29

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Sr. Product Engineer - National Imagery

At Esri - Remote / Flexible

Posted on Oct 15

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Software Development Lead Engineer - Waters Connect

At Waters - Bangalore

Posted on Oct 10

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Platform Engineer

At Aristocrat - Las Vegas

Posted on Oct 9

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Sr. Product Engineer - National Imagery

At Esri - Vienna

Posted on Sep 4

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Lead Design Engineer

Hyderabad, IndiaPosted Aug 9, 2026

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Development, automation and maintenance of EDA flows and scripts for physical implementation
Develop TFM to optimize PPA for IP's and Soft Controllers
PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
Candidate will be working on automation of Full chip floorplanning using latest AI tools. Involving in active AI agent based partition for Full Chip Floorplanning.
Required skills -
Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 5 + years' experience
Physical design experience in ASIC design environment
Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
Should have excellent leadership, communication, analytical and problem solving skills.
Expertise on High frequency design methodologies for complete ASIC backend flows.
Candidate with experience in Full Chip (SoC level) floorplanning, pin assignment, global clock distribution across all subsystems is a plus point.
Good communication skills, strong analytical problem solving skills and willingness to learn quickly.
Solid scripting skills including Python and Tcl.
Should be self-motivated and good team player.

We're doing work that matters. Help us solve what others can't.

About Cadence

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology

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