10,670 jobs for "Design Engineer"

RTL2GDS IC Design Engineer Architect

At Cadence - San Jose

Posted on Nov 5

View job Apply on company site

Senior Electrical Design Engineer

At Schneider Electric - Monterrey

Posted on Nov 6

View job Apply on company site

Product Design Engineer - Vision Pro

At Apple

Posted on Oct 19

View job Apply on company site

Embedded Design Engineer

At Leidos - Huntsville

Posted on Oct 28

View job Apply on company site

Senior Mechanical Design Engineer

At Eaton - Shanghai

Posted on Nov 8

View job Apply on company site

Senior Hardware Design Engineer - PCB Design

At General Motors - Sunnyvale · Warren

Posted on Oct 22

View job Apply on company site

Engineer 1 - Transformer Design Engineer

At GE Vernova - Clearwater

Posted on Nov 2

View job Apply on company site

Senior/Principal R&D RF/Microwave/Sensor Design Engineer, Onsite

At Sandia National Laboratories

Posted on Oct 15

View job Apply on company site

Internship - Design Engineer

At ASML - Wilton

Posted on Oct 28

View job Apply on company site

Product Design / Product Engineer/ Specialist

At Cummins - Pune

Posted on Oct 15

View job Apply on company site

LCON | Producibility Design Engineer | Derby/ Britstol

At Infosys - Derby

Posted on Oct 21

View job Apply on company site

Mechanical Design Engineer II

At Applied Materials - Bangalore

Posted on Nov 6

View job Apply on company site

Senior Electrical Power Design Engineer

At General Motors - Sunnyvale · Warren

Posted on Oct 22

View job Apply on company site

Network Routing Design Engineer Senior

At Leidos - Quantico

Posted on Oct 27

View job Apply on company site

Product Design Engineer

At Schneider Electric - Huntington

Posted on Nov 5

View job Apply on company site

Mechanical Design Engineer

At Applied Materials - Santa Clara

Posted on Oct 31

View job Apply on company site

Mechanical Design Engineer - Lead Steam Turbine Structure LP Hood Engineer (m/f/d)

At GE Vernova - Schenectady

Posted on Nov 2

View job Apply on company site

ENGLD|Mechanical Design Engineer| Gas Turbine Components

At Infosys - Derby

Posted on Oct 21

View job Apply on company site

Senior Design Engineer

At Eaton - Worcester

Posted on Nov 8

View job Apply on company site

In-Region Product Design Engineer - ( Mechanical)

At Apple

Posted on Oct 19

View job Apply on company site

Cadence

RTL2GDS IC Design Engineer Architect

San Jose$185,500 – $344,500Posted 2 days ago

Apply on company site View full job

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

◦ The ideal candidate will be energetic, innovative, and enthusiastic about helping customers solve their toughest Digital Implementation and Signoff challenges using Cadence technology. The candidate will drive RTL-to-GDS design activities at advanced process nodes using Cadence Digital IC products.

• Key Responsibilities

◦ Provide technical support to Cadence customers in Digital Design Implementation and Signoff, including synthesis, floorplanning, placement, clock tree synthesis, routing, design closure, static timing analysis, power integrity, and timing/power signoff.

◦ Lead block, subsystem, or full-chip RTL-to-GDS implementation from synthesized RTL or netlist through final GDS and design-database handoff.

◦ Guide customers on how to best utilize Cadence technologies to achieve PPA, signoff-quality, and project-schedule goals.

◦ Define and review hierarchical implementation strategies, floorplans, voltage areas, macro placement, IO and bump planning, utilization, congestion, and routability objectives.

◦ Drive placement, optimization, CTS, multi-source CTS or clock-mesh implementation, routing, extraction, ECO, and post-route closure.

◦ Own static timing analysis and timing-signoff methodology across multi-mode, multi-corner scenarios, including constraint quality, scenario coverage, timing-model consistency, and exception governance.

◦ Debug setup, hold, recovery/removal, clock-gating, transition, capacitance, pulse-width, and other applicable timing violations.

◦ Review clocks, generated clocks, clock-domain relationships, case analysis, false paths, multicycle paths, latency, uncertainty, derates, OCV methodology, propagated clocks, and SI-aware timing analysis.

◦ Drive correlation between implementation and signoff environments and establish repeatable timing-debug, reporting, and ECO-closure procedures.

◦ Support UPF-based low-power implementation, including voltage domains, isolation, retention, level shifters, and power switches.

◦ Define or review power-grid implementation and support static, dynamic, vectorless, and vectored IR/EM analysis and closure.

◦ Drive extraction, STA, LEC, CLP, IR/EM, DRC, and applicable LVS or layout-signoff flows, including issue disposition and closure evidence.

◦ Conduct technical presentations, design reviews, and product demonstrations.

◦ Drive technical evaluations and benchmarks to successful completion.

◦ Work closely with R&D to enhance tools and methodologies to meet and exceed customer requirements.

◦ Drive adoption and proliferation of Cadence tools and technologies.

◦ Amend and augment implementation and signoff flows using Tcl, Python, shell, or other programming skills to meet objectives and improve flow quality, reproducibility, and results.

◦ Capture best practices and lessons learned from evaluations, benchmarks, and customer engagements, and apply them to improve the efficiency and success rate of future engagements.

◦ Define tapeout-quality acceptance criteria and ensure complete, reproducible handoff of design databases, GDS, scripts, reports, checklists, assumptions, waivers, and known limitations.

◦ Provide technical support when developing business cases for process-improvement and methodology-development projects.

◦ Provide mentorship and technical guidance to junior engineers.

• Qualifications and Experience

◦ Requires a BS, MS, or PhD in Electrical Engineering or a related field, with 15-17 years of industry experience in design and EDA, focused on Digital Implementation and Signoff.

◦ Deep understanding of the ASIC RTL-to-GDS implementation process and signoff requirements.

◦ Strong hands-on experience with Place and Route tools such as Cadence Innovus, Synopsys ICC2, or Fusion Compiler.

◦ Experience with synthesis tools such as Cadence Genus or RTL Compiler, or Synopsys Design Compiler.

◦ Experience with EDA tools used in IC digital implementation and signoff flows, including STA tools such as Cadence Tempus or Synopsys PrimeTime.

◦ Strong STA and SDC debugging abilities are required, including MMMC analysis, timing exceptions, OCV-based analysis, clock modeling, SI effects, and implementation-to-signoff correlation.

◦ Experience with low-power analysis, UPF, multi-voltage design, clock design and analysis, and advanced 7 nm or 5 nm technology nodes is a plus.

◦ Experience with power-grid design, extraction, IR/EM analysis, LEC, CLP, DRC, and tapeout-quality physical verification is preferred.

◦ Automation skills using Python, Tcl, and shell scripting are essential.

◦ Strong analytical and debug skills covering digital implementation and signoff are critical.

◦ Proven track record of working effectively in a fast-paced, customer-facing environment.

◦ Excellent customer interaction, technical communication, and presentation skills.

The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.

About Cadence

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology

View company profile