20 jobs for "ASIC Digital Design Engineer Lead"

ASIC Digital Design Engineer Lead

At Apple - Austin

Posted on Oct 6

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ASIC Digital Design Engineer Lead

At Apple - Austin

Posted on Oct 6

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ASIC Digital Design Engineer Lead

At Apple - Austin

Posted on Oct 6

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Camera Image Sensor Digital Design Engineer Lead

At Apple - Cupertino

Posted on Oct 11

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Lead Design Engineer

At Cadence - Hyderabad

Posted on Aug 9

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Lead Design Engineer

At Cadence - Pune

Posted on Feb 19

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Sr Application Engineer

At Cadence - Penang

Posted on Oct 14

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Lead Design Engineer

At Cadence - Bangalore

Posted on Oct 16

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Sr. IC Package Design Engineer (Silicon Engineering)

At SpaceX - Austin

Posted on Oct 23

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Sr. IC Package Design Engineer (Silicon Engineering)

At SpaceX - Irvine

Posted on Oct 23

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 15

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Principal Design Engineer

At Cadence - Austin

Posted on Oct 1

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Design Engineer II

At Cadence - Hyderabad

Posted on Aug 9

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Principal Design Engineer

At Cadence - Austin

Posted on Oct 1

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

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Principal Design Engineer

At Cadence - Bangalore

Posted on Jun 23

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

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SoC Physical Design Verification Engineer

At Apple - Austin

Posted on Oct 8

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Design Engineer II

Hyderabad, IndiaPosted Aug 9, 2026

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Development, automation and maintenance of EDA flows and scripts for physical implementation
Develop TFM to optimize PPA for IP's and Soft Controllers
PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
Develop automation scripts using AI tools and reduce design execution turnaround time
Required skills -
Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years' experience
Physical design experience in ASIC design environment
Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
Prior experience in Logic Synthesis and PPA optimization techniques, Logic Equivalence Checks ( LEC ) debug experience for production designs
A detailed understanding of synthesis flows, hands on experience in developing, debugging synthesis flows with EDA tools such as Genus, Fusion Compiler.
Should have excellent leadership, communication, analytical and problem solving skills
Solid scripting skills including Python and Tcl.
Should be self-motivated and good team player.

We're doing work that matters. Help us solve what others can't.

About Cadence

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology

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