At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Formal Lead Application Engineer , Bangalore or Noida or Hyderabad.
The Opportunity
As a Formal Verification Lead Application Engineer, you'll perform the formal verification of design for complex IP's, subsystems and SoC's by using Jasper App's.
You will also help in define and improve design and verification methodologies that allow you to achieve formal verification closure. In this role, you will be responsible to partner with customers in top semiconductor companies to build unique and innovative formal solutions to verify cutting edge designs This involves working closely with the customers to develop efficient Formal methodologies, helping them leverage the latest Jasper features and capabilities and guiding them to achieve the target metrics. In this role you will be closely working with the R&D team to drive new capabilities/features which will help solve customer pain points and improve productivity. This an excellent opportunity to work in a friendly work environment with a team that is dedicated and passionate about technology and innovation. Wide range of problems to be solved, No repetitive work . Also role provides great opportunity to work on (develop) very important soft-skills and inter-personal skills needed for professional growth
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Requirements
• B.Tech./M.Tech. or equivalent in Electrical, Electronics or Computer Engineering.
• At least 8+ years of direct experience in formal verification.
• Ability to identify the suitable design for FV and analyze its complexity.
• Experience of creating formal test plan and test bench containing list of required checkers.
• Ability to dive deep in the RTL structures to understand the design and debug problems.
• Experience with CDC, LP , Security formal is a plus.
• Experience of at least one industry-wide used formal tools such as JG, VC Formal or Questa Formal.
• Proficient in SV and SVA.
• Perl/python/TCL scripting is a plus.
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