Verification Platform Engineer, Platform Architecture
19 days ago Austin, TX
About us
Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.
- Size: 10,000+ employees
- Industry: Technology
Apple's Platform Architecture group develops the next generation of Apple hardware and the tools to make it possible. Our team builds high-performance verification systems that accelerate the development of Apple silicon. We aim to push the boundaries of pre-silicon validation with simulation solutions that apply and extend principles from hardware emulation.
Description
This role bridges Apple's next-generation platform technology with DV methodology and tooling.
We are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping solutions. In this role, you will enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.","responsibilities":"Own engagements with silicon engineering groups to evaluate, integrate, and maintain high performance RTL simulation tooling.
Modify testbench and design RTL for tool compatibility and simulation efficiency.
Use internal and external EDA tools (e.g., RTL simulation tools, Logic Equivalence Checking [LEC], wave dumps, design libraries) to diagnose issues and explore design alternatives.
Design and integrate infrastructure improvements for faster simulation turnaround after RTL changes.
Partner closely (or embed) with internal teams for focused, high-impact engagements.
Occasionally travel (approximately once a year) to collaborate with development groups within the US.
Preferred Qualifications
Master's degree in Computer Engineering, Electrical Engineering, or another hardware-related field.
3+ years of relevant experience.
Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture).
Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows.
Strong understanding of SystemVerilog simulation semantics (events, time, glitches); intuitive grasp for hardware representation (clocks, resets, latches).
Strong communication skills, with a proven history of cross-functional collaboration across silicon engineering, design verification, and EDA development teams and organizational boundaries.
Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration / emulation.
Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers.
Minimum Qualifications
Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
Experience with SystemVerilog and EDA tooling.
Experience with software development (e.g., using C++) and scripting (e.g., Perl or Python).
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $225,300, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Description
This role bridges Apple's next-generation platform technology with DV methodology and tooling.
We are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping solutions. In this role, you will enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.","responsibilities":"Own engagements with silicon engineering groups to evaluate, integrate, and maintain high performance RTL simulation tooling.
Modify testbench and design RTL for tool compatibility and simulation efficiency.
Use internal and external EDA tools (e.g., RTL simulation tools, Logic Equivalence Checking [LEC], wave dumps, design libraries) to diagnose issues and explore design alternatives.
Design and integrate infrastructure improvements for faster simulation turnaround after RTL changes.
Partner closely (or embed) with internal teams for focused, high-impact engagements.
Occasionally travel (approximately once a year) to collaborate with development groups within the US.
Preferred Qualifications
Master's degree in Computer Engineering, Electrical Engineering, or another hardware-related field.
3+ years of relevant experience.
Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture).
Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows.
Strong understanding of SystemVerilog simulation semantics (events, time, glitches); intuitive grasp for hardware representation (clocks, resets, latches).
Strong communication skills, with a proven history of cross-functional collaboration across silicon engineering, design verification, and EDA development teams and organizational boundaries.
Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration / emulation.
Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers.
Minimum Qualifications
Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
Experience with SystemVerilog and EDA tooling.
Experience with software development (e.g., using C++) and scripting (e.g., Perl or Python).
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $225,300, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Additional Information
- Salary: $150,400 – $225,300
- Posted: 19 days ago