PMU Analog Layout Design Intern (m/f/d)
Oct 3, 2026 Munich, Germany
About us
Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.
- Size: 10,000+ employees
- Industry: Technology
The Silicon Engineering team is looking for a motivated intern (m/f/d) in Custom Analog Layout who wants to gain hands-on experience in chip design. You will support our Power Management team in developing analog ICs that power millions of Apple products around the world. Working closely with experienced layout engineers and circuit designers, you'll get exposure to the full layout and verification flow used in modern sub-micron CMOS technologies.
Description
• Support transistor-level layout of analog circuit blocks under the guidance of experienced colleagues
• Assist with layout verification (DRC, LVS, PERC, DFM) using Siemens EDA (Calibre)
• Gain insight into block- and top-level floor-planning together with the design team
• Analyse and document layout results and support design reviews
• Learn layout techniques for device matching, minimising parasitics, and power routing
Preferred Qualifications
Ideally some initial exposure to layout tools such as Cadence Virtuoso or similar full-custom environments
Minimum Qualifications
Currently enrolled student (m/f/d) in Electrical Engineering, Microelectronics, or a related field
Basic knowledge of semiconductor technology / CMOS circuits, e.g. from coursework or projects
Analytical mindset, attention to detail, and enjoyment of precise, hands-on work
Basic familiarity with Unix/Linux command-line environments
English language fluency (both written and verbal)
Team player with strong communication skills for working across disciplines
Description
• Support transistor-level layout of analog circuit blocks under the guidance of experienced colleagues
• Assist with layout verification (DRC, LVS, PERC, DFM) using Siemens EDA (Calibre)
• Gain insight into block- and top-level floor-planning together with the design team
• Analyse and document layout results and support design reviews
• Learn layout techniques for device matching, minimising parasitics, and power routing
Preferred Qualifications
Ideally some initial exposure to layout tools such as Cadence Virtuoso or similar full-custom environments
Minimum Qualifications
Currently enrolled student (m/f/d) in Electrical Engineering, Microelectronics, or a related field
Basic knowledge of semiconductor technology / CMOS circuits, e.g. from coursework or projects
Analytical mindset, attention to detail, and enjoyment of precise, hands-on work
Basic familiarity with Unix/Linux command-line environments
English language fluency (both written and verbal)
Team player with strong communication skills for working across disciplines
Additional Information
- Posted: Oct 3, 2026