Physical Design Sign-off Engineer
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power the Signoff infrastructure across all Apple SOC design groups within the Hardware Tech group. Signoff is the critical final verification stage in chip design where designs are validated against manufacturing, timing, and power criteria before tapeout. This role focuses on building and enhancing Signoff dashboards, CAD flow metrics collection, and data visualization tools that design and CAD teams rely on daily. You'll also participate in the development of our Signoff AI assistant and integrate modern AI/RAG capabilities into our platform.
Description
The Signoff Infrastructure developer will develop, support, and enhance the Signoff dashboards, CAD flow metrics collection, and visualization tools used for Signoff by all Apple SOC design groups. We are looking for a passionate, self-driven software engineer with the ability to work on complex software, a team player who pays a high level of attention to detail, strives for software quality, and prefers a test-driven development approach. The role requires providing Signoff infrastructure support and interfacing with the design and CAD teams to develop high-impact web applications to improve our Signoff process. You'll work across the full stack using Python and JavaScript/TypeScript, build and maintain backend services and APIs, develop interactive frontend dashboards, and work with SQL databases to manage and query enterprise-scale design data. As our platform evolves, you'll also contribute to integrating RAG and AI-powered features to enhance how teams discover and interact with Signoff data.
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Preferred Qualifications
Background in Chip Design, Chip Verification, or CAD
Experience with embedding models and LLM integration patterns
Understanding of RAG pipelines, including embeddings, chunking, and retrieval optimization
Experience with vector databases
Experience with containers and Kubernetes
Experience with monitoring and observability tools (Prometheus, Grafana)
Test-driven development experience in production environments
Minimum Qualifications
BS in Computer Science or related field with 10+ years of relevant industry experience
Proficient in programming using Python, Perl or Tcl
Hands-on experience with industry PNR and timing tools such as Cadence Innovus, Synopsys ICC2 / Fusion Compiler, PrimeTime, or Tempus
Experience taking block-level or chip-level designs through physical implementation and signoff closure on production silicon
Experience in timing closure, signal integrity, low-power design techniques, and clock-tree construction
Excellent communication skills and ability to collaborate across design, CAD, and technology teams
Understanding of tradeoffs to meet PPA (power, performance, area) targets, and experience defining implementation recipes to improve PPA
Perks and Benefits
Health and Wellness
Parental Benefits
Work Flexibility
Office Life and Perks
Vacation and Time Off
Financial and Retirement
Professional Development
Diversity and Inclusion
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