Posted: Oct 5, 2021
Role Number: 200051976
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU. You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be realizing the complete physical design verification closure from early design planning to tapeout. You will have hands on experience in physical design and large chip integration.
- We value proven ability in all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- Experience at full chip with configuration, methodology, and analysis of physical design verification checks: DRC, LVS, ERC, Process ANT, PERC, and ESD. Background with top to block correlation and reporting is required.
- Your knowledge in general partition PNR flow will serve you well in understanding how to support partition owners in solving physical design verification issues.
- Familiar with hierarchical design approach, and techniques that enable physical design verification that is correct by construction. Familiar with GDS assembly, GDS requirements for hard macros.
- Your depth of expertise on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain will serve you well.
- Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying innovative technologies.
- From a CAD tool perspective, experience with Floorplanning tools, P&R flows, mainstream Physical Design Verification tools (e.g. Mentor) is required. Familiar with TCL scripting.
Work closely with FE team to understand chip architecture and drive physical verification aspects early in the design cycle. Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress while offering physical verification support. Be focal point for all things PDV, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, power integrity, and PNR. Manage and resolve design and flow issues related to physical design, identify potential solutions and drive execution. Are you a confident problem solver who thrives under pressure to find new, creative solutions? Are you ready to help chart the future of Apple's ecosystem? If so, we are excited to hear from you!
Education & Experience
MSEE or equivalent is required.