FE Engineer
19 days ago Sunnyvale, CA
About us
Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.
- Size: 10,000+ employees
- Industry: Technology
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day.
As a SoC Front End Design Integration Engineer you will be designing, integrating, and verifying a system fabric bus into a subsystem. In this role, you will need to define and build this platform with flexibility and reusability in mind.
Description
* Building a test bench, creating test vectors, and running the verification environment to verify that the subsystem you designed works properly
* Synthesize the subsystem into logic and perform Static Timing Analysis (STA) on the design to make sure it meets the timing requirements
* Designing, integrating, and verifying a system fabric bus into a subsystem
Preferred Qualifications
* Experience/exposure writing specifications and documentation
* Experience/exposure with verifying logic design hardware
* Experience/exposure to front-end tools and methodologies
Minimum Qualifications
Digital Logic Design knowledge
Verilog/System Verilog RTL language design entry
Synopsys/Cadence synthesis
Synopsys PrimeTime Static Timing Analysis (STA)
Synopsys (VCS)/Cadence(Incisive) simulation
Strong problem solving and analytical skills
Strong communication skills combined with team-oriented approaches to own the verification efforts in a specific area of the design
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
As a SoC Front End Design Integration Engineer you will be designing, integrating, and verifying a system fabric bus into a subsystem. In this role, you will need to define and build this platform with flexibility and reusability in mind.
Description
* Building a test bench, creating test vectors, and running the verification environment to verify that the subsystem you designed works properly
* Synthesize the subsystem into logic and perform Static Timing Analysis (STA) on the design to make sure it meets the timing requirements
* Designing, integrating, and verifying a system fabric bus into a subsystem
Preferred Qualifications
* Experience/exposure writing specifications and documentation
* Experience/exposure with verifying logic design hardware
* Experience/exposure to front-end tools and methodologies
Minimum Qualifications
Digital Logic Design knowledge
Verilog/System Verilog RTL language design entry
Synopsys/Cadence synthesis
Synopsys PrimeTime Static Timing Analysis (STA)
Synopsys (VCS)/Cadence(Incisive) simulation
Strong problem solving and analytical skills
Strong communication skills combined with team-oriented approaches to own the verification efforts in a specific area of the design
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Additional Information
- Salary: $129,300 – $194,700
- Posted: 19 days ago