Experienced GPU Top Level Physical Design Engineer
25 days ago Cambridge, United Kingdom
About us
Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.
- Size: 10,000+ employees
- Industry: Technology
Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPUs! You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices!
Join us!
Description
This role requires a mix of strategic engineering along with hands-on, technical work, being responsible for implementing complete chip design from netlist to tapeout and having hands on experience in physical design and large chip integration.","responsibilities":"• Collaborate with FE team to understand chip architecture and drive physical aspects early in design cycle.
• Contribute to innovation with the physical design team and develop methodologies and "best known methods" that will enable outstanding GPU design.
• Develop PD guidelines and checklists and drive execution. Be the focal point for place and route integration at the top level • Plan short and long-term work and goals with awareness of dependencies between different domains like top, STA, block place and route.
• Reach new career highs as you resolve design and flow issues related to physical design, identify potential solutions and drive execution.
• If you are a confident problem solver who thrives under pressure to find new, creative solutions, we are excited to hear from you!
Preferred Qualifications
Knowledge of issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
Depth of expertise on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand-new technologies.
Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.
Minimum Qualifications
MSEE or equivalent is required.
Deep experience with all aspects of ASIC integration including Floorplanning, Clock & Power distribution, global signal planning, I/O planning & hard IP integration.
Join us!
Description
This role requires a mix of strategic engineering along with hands-on, technical work, being responsible for implementing complete chip design from netlist to tapeout and having hands on experience in physical design and large chip integration.","responsibilities":"• Collaborate with FE team to understand chip architecture and drive physical aspects early in design cycle.
• Contribute to innovation with the physical design team and develop methodologies and "best known methods" that will enable outstanding GPU design.
• Develop PD guidelines and checklists and drive execution. Be the focal point for place and route integration at the top level • Plan short and long-term work and goals with awareness of dependencies between different domains like top, STA, block place and route.
• Reach new career highs as you resolve design and flow issues related to physical design, identify potential solutions and drive execution.
• If you are a confident problem solver who thrives under pressure to find new, creative solutions, we are excited to hear from you!
Preferred Qualifications
Knowledge of issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
Depth of expertise on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand-new technologies.
Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.
Minimum Qualifications
MSEE or equivalent is required.
Deep experience with all aspects of ASIC integration including Floorplanning, Clock & Power distribution, global signal planning, I/O planning & hard IP integration.
Additional Information
- Posted: 25 days ago