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Sr Principal Software Engineer, Innovus - Physical Synthesis & Optimization

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Software Engineer II: AI Agents Hardware Verification

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Lead Design Engineer - Verification

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Software Engineer II: AI Inhouse Adoption

At Cadence - Belo Horizonte

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Design Engineer II

Noida, IndiaPosted Oct 1, 2026

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Overview:

Key Responsibilities:

Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis.
Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

Required Qualifications:

B.Tech/M.Tech in ECE with
Experience in SystemVerilog/UVM and C/C++ for architectural modeling.
Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.

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About Cadence

Cadence is a pivotal leader in computational software.

Size: 10,000+ employees
Industry: Technology

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