Verification Engineer

  • Position title: SoC ASIC Verification Engineer
  • Responsibilities:
    • Instrumental in the development of infrastructure for the validation of ARM AMBA-based or DSP-based architectures and the verification of SoC/ASIC hardware.
    • Additional duties include the development of directed and random hardware verification environments, and the application of those environments to SOC/ASIC verification
    • Integration of VIP and functional verification agents in UVM verification environment to support coverage-driven verification
  • Qualification:
    • Verification experience on SoC or ASIC chips
    • Experience with high level verification environments/languages such as UVM, VMM, SystemVerilog or Vera
    • Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models
    • Strong C/C++ programming software background is preferred
    • Shell scripts and Perl/Python expertise, create runsim, lsf, regression management scripts
    • Able to understand Verilog/SystemVerilog RTL code, debug simulation errors, identify and fix RTL/Testbench issues
    • Audio & voice DSP background is preferred

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