Staff ASIC Design Engineer

About Synaptics:

Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics' broad portfolio of touch, display, biometrics, voice, audio, and multimedia products is built on the company's rich R&D, extensive IP and dependable supply chain capabilities. With solutions designed for mobile, PC, smart home, and automotive industries, Synaptics combines ease of use, functionality and aesthetics to enable products that help make our digital lives more productive, secure and enjoyable. (NASDAQ: SYNA ) www.synaptics.com .

Job Scope:

The Multimedia Silicon R&D team is searching for a hands-on, team oriented engineer with front-end ASIC/FPGA RTL design expertise. In this individual contributor role, candidate will have complete ownership of ASIC RTL designs from specification to silicon validation. Candidate should have hands-on knowledge of Micro-Architecture design, ASIC/FPGA RTL design, Functional Simulation, Synthesis, Formal Verification, CDC Analysis and Static Timing Analysis. Candidate should have strong ability to learn and explore new technologies, FPGA/ASIC CAD tools and ability to demonstrate good analysis and problem-solving skills. Candidate must have the ability to multi-task, thus ensuring timely completion of several complex independent tasks.

Job Responsibilities

Candidate will be responsible for combination of following executables:

  • Study of Functional Specification/Requirement documents, Standard documents
  • Micro-Architecture understanding/development for existing/new designs
  • Creation and maintenance of design specifications & documentation
  • RTL design/upgradation of video/audio processing algorithms, video/audio subsystems
  • Power aware RTL coding/design
  • Verilog/SystemVerilog/VHDL RTL design of [FSM, Complex Data path/Control Path Designs]
  • Coding C-wrappers, C-functions for C-vs-RTL simulations
  • Block/System-level Functional and logical Verification using C-vs-RTL approach
  • Clock-Structure design, Synthesis/STA Constraint modelling/validation
  • Logic Synthesis (using Design-Compiler or equivalent)
  • Formal Verification (using Conformal or equivalent)
  • CDC (using Spyglass)
  • Static Timing Analysis (using Primetime or Encounter Timing System)
  • FPGA prototyping
  • FPGA/Silicon/System validation, debug
  • Interaction/co-ordination with different cross-functional (design/verification/validation/software) teams across different world geographies


Job Qualifications
  • At least9+ yearsof ASIC Design withgood working understanding/experience/knowledgeof following is must:
    • ASIC/FPGA RTL design using HDL languages like VerilogHDL, VHDL, SystemVerilog
    • AXI3/AXI4, AHB Standards/Protocols
    • Audio, HDMI-Video specification/standards/protocols
    • Various Video, Audio formats
    • Simulator tools: VCS, Questa
    • ASIC Flow tools: Design Compiler(T), Formality, PrimeTime
    • Waveform viewer tool: Verdi
    • C, C++ language
    • Scripting: Perl, Tcl, Shell
    • SoC Designs
    • Clock-Structures/Schemes
  • Following skills are desirable:
    • Strong Analytical, Problem solving, Debugging skills
    • Excellent Oral/Written Communication Skills
  • Following additional skills a plus:
    • Low power design methodology & techniques
    • DFT Techniques Knowledge
    • Timing closure experience of minimum 2 tape-out cycles
    • Emulation
  • BE/BTech/ME/MTech in Electrical/Electronics/VLSI Design/Communications/Image processing/Audio processing/DSP or a related technical discipline


Synaptics is an Equal Opportunity Employer


Back to top