Sr. Verification Engineer

About Synaptics

Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics' broad portfolio of touch, display, and biometrics products is built on the company's rich R&D and supply chain capabilities. With solutions designed for mobile, PC and automotive industries, Synaptics combines ease of use, functionality and aesthetics to enable products that help make our digital lives more productive, secure and enjoyable. (NASDAQ: SYNA)

Job Responsibilities

  • Work closely with the team, review specifications, develop attributes, tests & coverage plans, define methodology & test benches.
  • Work closely with design & micro-architecture teams to understand the functional & performance goals of the design.
  • Architect block and full-chip verification environments using system Verilog and constrained random techniques for SOCs with embedded MCU
  • Develop test plans and coverage metrics from specifications and write block and chip-level tests
  • Debug RTL and Gate simulations and work with design engineers to verify fixes
  • Create test cases and write diagnostics for validation of prototype (pre-tape out) and ASIC
  • Replicate silicon bugs in simulation environment and validate fixes or SW workarounds
  • Convert verification tests to test patterns and assist Test Engineers on ATE vector bring up
  • Work independently and manage deliverables to align with the project goals and cross functional coverage
  • Evaluate latest verification methodologies and develop scripts for automate verification flows.

Required Qualifications

  • BSEE with 5+ years or MSEE with 3+ years in IC verification
  • Exposure to different sensor HW(proximity, touch, haptics) and all general peripheral device protocol( I2C, UART, SPI, USB etc.)
  • Advanced knowledge of SOC/Display & System architecture/design & in-depth knowledge of the state of the art verification flow.
  • Experience with low-level programming in C/C /assembly.
  • Familiarity with verification environments, VMM, UVM System Verilog is a plus.
  • Knowledge of industry standard interfaces, good understanding of Verilog, Verilog simulator and debug.
  • Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy (SVA)
  • Should be a team player with excellent communication skills and the desire to take on diverse challenges.

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