Sr. Staff ASIC Design Engineer

About Synaptics

Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics' broad portfolio of touch, display, biometrics, voice, audio, and multimedia products is built on the company's rich R&D, extensive IP, and dependable supply chain capabilities. With solutions designed for mobile, PC, smart home, and automotive industries, Synaptics combines ease of use, functionality, and aesthetics to enable products that help make our digital lives more productive, secure, and enjoyable. (NASDAQ: SYNA)

The IoT Multimedia division at Synaptics delivers advanced media processing technology solutions for video and audio applications for the home entertainment market. The employee will have the opportunity to join the silicon design team in the multimedia group that develops Set-top-box, streaming, media products such as Chromecast and other connected products.

The candidate will be responsible for SoC Design/Integration, defining and creating clock/reset logic for the chip, coming up with full-chip pad ring, Synthesis, Equivalence Check, linting/CDC Analysis, and Static Timing Analysis for multi-million gate SoCs targeted for Voice Assistant & Multimedia applications. The candidate will also be responsible for RTL/gate level Power Analysis and Optimization. Would work with other members of the team to optimize the PPA in creating the most cost effective SoCs.


  • BSEE/MSEE with 12+ years of experience
  • Must have hands on experience with SoC design and integration for complex SoCs
  • Must have hands on experience with Verilog Coding
  • Must have hands on experience with Logic Synthesis using Design Compiler and Static Timing Analysis with Prime Time
  • Working knowledge of integrating IP blocks with AMBA AXI/AHB interfaces to SoC Fabric and performance analysis is a strong plus
  • Experience with PERL scripting in creating and maintaining the EDA tool flows is a big plus
  • Experience with creating pad ring and working on chip-level floor-plan is a strong plus
  • Must have hands on experience with constructing full-chip IO pad ring from foundry pad library. Must be proficient in directly working with foundry to come up with the rules in building the pad ring
  • Any experience with automating pad ring generation from chip IO pinlist file is a strong plus
  • Knowledge of chip reset and clock design is a strong plus
  • Knowledge of dynamic power analysis of the chip is a strong plus


Back to top