Sr. Implementation Engineer

Job Description

  • Design/verification of SoC-level logic including clock, reset.
  • All DFT related rtl level logics include Pinmux, Scan, At Speed Scan, Mbist, Boundary scan, and Testbus design and verification.
  • Physical implementation including chip synthesis and all DFT related logic insertion and verification.
  • Timing constraint/SDC develop and timing closure at functional reg to reg and IO/DFT timing, crosstalk analysis, etc.
  • Support product testing and debug manufacture failures.
  • Low power design includes power analysis, architecture definition and methodology development.
  • Scripting, Unix shell, TCL

Qualifications
  • BSEE/MSEE + 3-5 years hands on SOC integration or Physical Implementation
  • Good skill of English for reading, writing.
  • RTL design and synthesis.
  • Experience of supporting DFT.
  • Experience on Static timing, timing closure, and noise analysis.
  • Experience on Cadence EPS and CPF flow will be a plus.


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