Sr. Digital IC Design Engineer

About Synaptics

Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics’ broad portfolio of touch, display, and biometrics products is built on the company’s rich R&D and supply chain capabilities. With solutions designed for mobile, PC and automotive industries, Synaptics combines ease of use, functionality and aesthetics to enable products that help make our digital lives more productive, secure and enjoyable. (NASDAQ: SYNA) www.synaptics.com.

Responsibilities:

  • Executes flows for synthesis, DFT insertion, LEC, CDC and LP checks in the next generation of Synaptics

devices

  • Performs micro architecture and design using RTL
  • Understand/analyze timing, area, and power tradeoffs for different technologies/libraries.
  • Good knowledge of tcl/make/python scripts.
  • Develop and debug constraints, RTL, clocks, and layout to achieve netlist synthesis and static timing

closure

  • Good knowledge of DFT concepts & ATPG Flows.
  • Implement and integrate Memory BIST, Logic Scan, Boundary Scan, and custom ATE and debug test

logic. Responsible for simulation and timing closure of DFT logic implementation

  • Work with physical design engineers to plan block layout, synthesize designs, formally check synthesis results, and achieve both block and full-chip timing closure
  • Participate in silicon characterization, debug and analysis

Requirements:

  • Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic

environment, able to create and implement new solutions where required

  • Hands on experience with Synthesis, CDC, DFT, MBIST, STA, LP checks, LEC. etc Front-End activities
  • Knowledge of planning and implementing SoC DFT features
  • Experience with industry standard ASIC implementation flows & tools
  • Works with external EDA vendors and internal Flow team for Enhancements of Flow.
  • Experience with USB, SPI.etc other Interface protocols timing is plus

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