Sr. CAD Engineer

About Synaptics

Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics' broad portfolio of touch, display, and biometrics products is built on the company's rich R&D and supply chain capabilities. With solutions designed for mobile, PC and automotive industries, Synaptics combines ease of use, functionality and aesthetics to enable products that help make our digital lives more productive, secure and enjoyable. (NASDAQ: SYNA)

Job Responsibilities

In this critical role as a member of our central CAD team, your primary responsible will be to develop and execute power EM/IR analysis and flows for transistor, mixed-signal and digital designs. You will be responsible for static/dynamic IR analysis, switch modeling and in-rush current analysis for our highly complex SOC chips. You will also have the opportunity to work on PDK management/deployment, CAD tool methodology and CAD flows related to circuit simulation, analog/digital implementation and physical verification.

Your Primary responsibilities include but not limited to the following:

  • Developing companywide IR/EM flows and related methodologies.
  • Execute block and chip level IR/EM analysis and present results
  • Drive IR/EM methodology improvements and improve flow quality
  • Install and Evaluate tools for IR/EM
  • Document, train and support other team members to execute IR/EM flows.
  • Work with tool vendors to debug and improve IR/EM tools.
  • Support PDK management/deployment and QA
  • Support physical verification and circuit simulation tools/flows
  • General CAD support for our global design teams

Required Qualifications

  • BSEE (MSEE preferred) with at least 5 years of experience in the relevant domain
  • Experience with Static/Dynamic IR/EM analysis of custom analog and gate level designs.
  • In depth knowledge and expertise with Ansys Totem/Redhawk or Cadence Voltus tools
  • Understanding of physical design, package and chip level co-designs concepts.
  • EM/IR tool validation and qualification
  • Dynamic circuit simulation
  • Setting up technology files for new PDK's, flow regression and release
  • Library characterization for EM/IR
  • Proficient in programing languages like Unix scripting, Perl/C/C++/Tcl/Python
  • Ability to work under pressure

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