Layout Design Engineer
Perform IC mask design, layout parasitic extraction, and physical verification on analog and mixed-signal circuits. The candidate will be responsible for independently planning and executing the layout, LPE, LVS and DRC on complex analog and mixed-signal integrated circuits. Travel is required as part of this role
- Minimum 2 years of experience in IC mask design.
- Must have experience in handling full chip layout using state-of-the-art IC layout tools.
- Must have job view experience.
- Understand how to protect sensitive nodes in an analog and mixed-signal circuit block.
- Experience in power/ground routing and decoupling capacitor placement.
- Familiar with ESD design rules, latchup design rules, antenna and EM rules.
- Experience with either Cadence Assura or Mentor Graphics Calibre physical verification tools is a must.
- Experience with Cadence Virtuoso is a must plus.
- Good communication skills in Mandarin and English are required.
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