Digital Design Engineer
- Develop verification testbench components for chip/module level using System Verilog, C & Perl
- Use high level language concepts (Object oriented, UVM/OVM/VMM etc) to develop extendable environment.
- Define and execute detailed verification plan from spec working with architects, designers, system engineers.
- Write tests, automate regression scripts and regression environment.
- Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
- Debug tests, run gate level simulations at unit/sdf delays
- Develop automated/scripted design flows for the above mentioned development processes
- Participate in FPGA/silicon debug and analysis
- Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required
- Excellent debugging skills in both SW and ASIC hardware
- Must be good in building verification environments preferably using the verification subset of high level languages like System Verilog (OVM, VMM), Specman, C/PLI etc.
- Must be proficient in Verilog (System Verilog preferred).
- Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
- Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy
- Good understanding of latest formal verification techniques, assertions, OOP etc is a plus.
- Understanding or prior experience with Industry standard protocols like USB, SPI, SATA, Ethernet, DisplayPort, SRIO etc is a definite plus
- Understanding or Prior Experience in ARM/Tensillica Processor platforms is a plus
- Good written and oral communication skills. Ability to clearly document plans.
- Ability to interface with different teams and prioritize work based on project needs.
- BE/B.Tech 10+ , MS +8 years or PhD in ECE
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