Design Verification Engineer

Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics' broad portfolio of touch, display, biometrics, voice, audio, and multimedia products is built on the company's rich R&D, extensive IP, and dependable supply chain capabilities. With solutions designed for mobile, PC, smart home, and automotive industries, Synaptics combines ease of use, functionality, and aesthetics to enable products that help make our digital lives more productive, secure, and enjoyable. (NASDAQ: SYNA)

Job Responsibilities
The employee will have the opportunity to join the Multimedia IoT silicon design team at Synaptics Inc. The multimedia IoT team at Synaptics develops cutting edge products for connected devices such as Set-top-box, Google Chromecast® and Google Home®.

The responsibilities for this position include functional verification at a block level, subsystem and usage of verification techniques such as constrained random testing, black box and white box testing concepts.

Besides functional simulation-based verification, the engineer will be responsible for doing gate level simulations, writing flow automation scripts, writing testplans, writing tests in native system verilog and also using VMM/UVM based methodology for new features or new IP blocks that need to be verified. The person will also be responsible for doing connectivity verification for analog blocks and debug of full chip regressions in multiple areas of the chip.

The candidate should have experience in writing scripts in PERL and Python, and also used a UNIX based operating system.

Job Qualifications

  • MSEE/CS with up to 3 years of experience
  • Expertise in System Verilog or equivalent object oriented verification methodology
  • Strong scripting skills in PERL, Python
  • Knowledge of C, C++ and conversant in UNIX
  • Experience in full chip verification techniques
  • Exposure to the various verification techniques such as coverage based verification, formal verification techniques etc.
  • Experience in writing tests/testplans and test bench components for both functional blocks and full chip


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