Design Verification Engineer
Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics' broad portfolio of touch, display, biometrics, voice, audio, and multimedia products is built on the company's rich R&D, extensive IP and dependable supply chain capabilities. With solutions designed for mobile, PC, smart home, and automotive industries, Synaptics combines ease of use, functionality and aesthetics to enable products that help make our digital lives more productive, secure and enjoyable. (NASDAQ: SYNA ) www.synaptics.com .
- Responsible for the execution of functional simulation-based verification at a block level, subsystem and full-chip using techniques such as constrained random testing, black box and white box testing concepts.
- Engage in gate level simulations, writing flow automation scripts, author test plans, write tests in native system Verilog or VMM/UVM based methodology for new features or new IP blocks that need to be verified.
- Verify connectivity for analog blocks and debug of full chip regressions in multiple areas of the chip
- Apply knowledge and understanding of system Verilog or equivalent object-oriented verification methodology for SOC verification.
- Perform programming and script development using C/C++, Python/PERL for verification tasks.
- Master's degree in Electrical Engineering or Computer Engineering
- One (1) year experience in system Verilog, UVM based constraint random tests, functional verification at both block level and full chip
- Script writing in Perl and Python.
Synaptics is an Equal Opportunity Employer
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