Design for Test Engineer
Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics' broad portfolio of touch, display, biometrics, voice, audio, and multimedia products is built on the company's rich R&D, extensive IP and dependable supply chain capabilities. With solutions designed for mobile, PC, smart home, and automotive industries, Synaptics combines ease of use, functionality and aesthetics to enable products that help make our digital lives more productive, secure and enjoyable.(NASDAQ: SYNA ) www.synaptics.com .
The candidate will be responsible for DFT architecture and the implementation of MBIST, SCAN, and BSCAN for multi-million gate SoCs targeted for Voice Assistant & Multimedia applications. Would work with other members of the team to drive DFT methodology and flow to make it more efficient. Would be responsible to synthesize/optimize the DFT logic for best PPA. Would be responsible for the Static Timing Closure for all the test logic in full-chip.
- BSEE/MSEE with 8+ years of experience
- Must have hands on experience with DFT architecture - DFT planning for complex multi-million gate SoCs.
- Must have hands on experience with Scan/EDT, MBIST, and Boundary Scan for complex multi-million gate SoCs in cutting edge process nodes.
- Must have hands on experience with creating iJTAG structure in Verilog
- Must have hands on experience with PERL scripting in creating and maintaining the EDA tool flows
- Hands on experience with Logic Synthesis and Static Timing Closure is a strong plus
- Working knowledge of Tessent tool flow is a strong plus
- Experience with creating pad ring and working on chip-level floor-plan is a strong plus
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