Design & Verification Engineer_SMTS - SISW-MG
- Greater Noida, India
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About group: Veloce Transactors (Accelerated Verification IPs) Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group is responsible for developing transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Group holds more than 25 protocol solution in its kitty and expanding further.
Primary responsibilities include -
- Understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesizable design using Verilog/System Verilog, verification.
- Individual must be able to guide the verification team to create verification test plans and environments, testcase development, VIP usage, and the ability to debug of defects found through verification processes.
- Individual would need to engage with customers for Deployment and R&D assistance.
- Exposure of object oriented programming using languages such as C++ is advantage Experience in scripting languages such as Perl,
- Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc.
Work Experience - 3 years +
Education - (BE/BTech/ME/MTech/MS) From any of the premier engineering institutes
Primary Technical skills:
- Understanding of verification tools like Simulator, Synthesis etc.
- Hands on experience on System Verilog, UVM, SystemC, RTL development.
- Understanding of some of the standard protocol interfaces like AMBA, PCIe, USB etc.
- Excellent written and verbal interpersonal skills
- Self-motivated and great teammate
Additional desirable skills and experience
- Knowledge of C/C++/Python programming languages
- Understanding of verification solutions beyond simulation like Emulation, Formal etc.
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time
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