Corporate Application Engineer (UVM, System Verilog, VHDL) - SISW 219609
- Austin, TX
At Siemens we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow's reality. Find out more about the Digital world of Siemens here: www.siemens.com/careers/digitalminds
Company: SISW - EDA
Job Title: Corporate Application Engineer (UVM, System Verilog, VHDL) - 219609
Job Category: Customer Support
The Corporate Applications Engineer is a dynamic, exciting position where you can utilize your hardware verification and
design skills to enable the success of our customers and our business. You will assist customers by deploying Mentor
Graphics' functional verification software, aiding them to solve complex verification and design challenges. Responsibilities
Troubleshooting technical obstacles to productivity with Mentor Graphics' software.
• Developing and delivering technical training on new features and product updates.
• Provide customer training on High Level Synthesis Products
• Perform Beta testing and collaborate with R&D to drive product direction and capabilities of HLS, RTL power optimization
and Formal Verification
• Tracking and updating customer issues using Mentor Graphics' processes and tracking tools.
• Developing technical content for Mentor Graphics' knowledge-base.
• Communicating customers' technical requirements as well as priority and impact, influencing the product team to meet
customer's needs and shape product direction.
• Work collaboratively with the customer and team members to ensure mutual success
• Developing positive, technical relationships with our customers, sales teams, and the product engineering teams.
• Some travel is required for support and training purposes
Experience with HDL-based, register-transfer-level (RTL), digital logic design, verification languages, and functional
verification methodology, for ASICs and/or FPGAs. Requirements include:
• Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design
• Knowledge of UVM is desired
• Knowledge of C/C++ is mandatory
• Experience of ASIC or FPGA hardware design and implementation using RTL or HLS tool flows
• Experience of RTL verification flows and methodologies
• Demonstrated proficiency with Object Oriented Programming or experience in test bench architecture and design in one or more of the following languages: SystemVerilog, Specman/e, Vera, Testbuilder
• Experience in constrained-random testing, simulation acceleration/emulation, assertions (PSL or SV), static formal
verification methods, including clock domain crossing verification and LINT or formal design checking methods is also desirable. Experience in UVM is desired
• Self-motivated, flexible and self-disciplined, and comfortable in a dynamic, quick-moving environment.
• Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales and product teams.
• Experience with support, sales, or marketing is desired
• BS in EE/CompE is required, MS in EE/CompE is desired.
Organization: Digital Industries
Company: Siemens Industry Software Inc.
Experience Level: Experienced Professional
Job Type: Full-time
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