Staff ASIC Digital Implementation Flow Developer

Northrop Grumman Mission Systems (NGMS) is seeking aStaff ASIC Digital Implementation Flow Developer for the Engineering, Sciences, and Technology (ES&T) Organization. The position is located at the Advanced Technology Lab (ATL) - just outside of Baltimore, Maryland - where we design, manufacture, and test semiconductor products for internal and commercial production as well as emerging programs.

At Northrop Grumman our ASIC Digital Implementation Flow Developers enjoy working on a variety of assignments across a broad range of topics and varying complexity. The ASIC Digital Implementation Flow Developer will be called in to lead the creation of new design flows and design capabilities by leveraging existing commercial tools, harnessing custom engineered scripts, and even working with EDA vendors on custom tools. He/she will also work closely with designers, developers, and physicists to understand what is needed and provide the appropriate support to help the team accomplish assigned goals and tasks.

As an ASIC Digital Implementation Flow Developer at Northrop Grumman you can also effect change in how we pursue advanced technology development. If you see a better way to do things, you WILL have the opportunity to make those changes here at Northrop Grumman.

The ideal candidate will have solid skills with software tools and data inputs typically used in the design of microelectronics ASICs and strong experience supporting successful design efforts that culminate in tapeouts.

Join us for the chance to work with an amazing, experienced, and talented team. We are expanding with new work on many development and production programs. If you want to work on a team where your coworkers are excited to come to work and solve problems, and where people are actively invested in their work, then Northrop Grumman's ATL is the right place for you.

Responsibilities include one of the following:

  • Define and lead the development of innovative and effective RQL (Reciprocal Quantum Logic) specific digital design flows specialized in static timing analysis (STA) and logic equivalency checking (LEC)
  • Define and lead the development of innovative and effective RQL (Reciprocal Quantum Logic) specific digital design flows specialized in static timing analysis (STA) and logic equivalency checking (LEC)
  • Define and lead the development of innovative and effective RQL (Reciprocal Quantum Logic) specific physical synthesis design flows with extensive knowledge of physical aware synthesis
  • Define and lead the development of innovative and effective RQL (Reciprocal Quantum Logic) specific timing engine for the front end digital design flows
Other responsibilities to include (but not limited to):
  • Collaborate with physicists, circuit designers and PDK engineers on library development and modeling to support the tool/flow
  • Understand and guide the use of configuration management
  • Using the agile process and internal tool development process to drive the project to the finish line
  • Provide design/CAD team strong scripting capabilities in SKILL, PERL, Ocean, Linux Shell, etc.
  • Interface with CAD tool vendors to prove out releases and flows, solve bugs, improve usability, etc.
  • Oversee the Installation of new software and software updates and perform flow signoff
  • Strong leadership and excellent verbal and written technical communication skills are required.
Basic Qualifications:
  • This job requires a Bachelor's degree in STEM related field or technical area (BSEE or other Engineering discipline preferred) with 14 years' of relevant ASIC experience, (relevant MS with12 years; 9 years with a PhD)
  • Proven ability to develop methodology for CMOS timing-driven synthesis from RTL to gate netlist
  • Expertise in developing synthesis methodology and design constraints (SDC) for aggressive speed, power and size constraints
  • Expertise in RTL architecture for aggressive speed, size and power constraints.
  • Expertise in architecting testability features for specialized circuits, for example specialize memories and analog circuits
  • Ability to manage change in a highly dynamic environment
  • Expertise in developing a methodology for Design for Test insertion
    • Synopsys Design Compiler, Cadence Genus
    • Synopsys DFT compiler, Cadence Genus scan insertion
    • Synopsys Tetramax, Cadence Modus
  • Ability to work collaboratively in a team
  • Experience interfacing with engineers and managers to schedule projects and provide schedule updates and roadmaps, must have strong written and oral communication skills

Preferred Qualifications:
  • Proficiency in the entire ASIC design flow from RTL through tape-out (RTL coding, simulation, synthesis, static timing analysis, logic equivalence check, DFT insertion)
  • Proficiency in static timing analysis
    • Synopsys Primetime, Cadence Tempus
  • Tool experience with Formal verification Synopsys Formality or Cadence Conformal
  • Familiarity with EDA standards used in cell/library development and modeling Liberty, LEF (library exchange format), DEF (design exchange format), OA (OpenAccess)
  • Ability to obtain and maintain a TS/SCI Level Clearance

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit . U.S. Citizenship is required for most positions.

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