Northrop Grumman is seeking PDK Engineers and Digital CAD Tool/Flow/Methodology Developers!
Northrop Grumman Mission Systems (NGMS) is actively hiring PDK Engineers and Digital CAD Tool/Flow/Methodology Developers for our Advanced Concepts & Technologies (AC&T) Organization. These positions are located just outside of Baltimore, MD at the Advanced Technology Lab (ATL) where we design, manufacture, and test semiconductor products for internal and commercial production as well as emerging programs.
Join us for the chance to work with an amazing, experienced, and talented team. We are expanding with new work on many development and production programs. If you want to work on a team where your coworkers are excited to come to work and solve problems, and where people are actively invested in their work, then Northrop Grumman's ATL is the right place for you.
As a member of our AC&T Team at Northrop Grumman you can also effect change in how we pursue advanced technology development. If you see a better way to do things, you WILL have the opportunity to make those changes here at Northrop Grumman.
The PDK team has a revolving collection of 80 production and development processes that we support at any time, and Northrop Grumman does not silo our PDK Engineers to one program or one task. Our PDK Engineers typically work on two or more different programs at once and have the opportunity to touch all areas of PDK development within those programs.
The ideal candidate will have solid process design kit (PDK) development skills and strong experience developing/augmenting/debugging process techfiles, P-Cells and design verification (DRC/LVS/PEX) rule files. Junior candidates will be able to leverage their knowledge of Cadence Virtuoso to develop solid process design kit (PDK) development skills with on the job training.
PDK Engineer Responsibilities include:
- Create & maintain PDK techfiles
- Create & maintain design verification rulefiles
- Create & maintain skill based P-Cells
- Create & maintain scripts to create CAD capabilities
- Peer review work of other PDK team members
- Create & maintain quality assurance capabilities to verify implementations
- Promote & implement best practices for PDK creation and maintenance tasks
- Create & maintain PDK documentation
The Digital Tool, Flow and Methodology Developer will be called in to lead the creation of new design flows and design capabilities by leveraging existing commercial tools, harnessing custom engineered scripts, and even working with EDA vendors on custom tools. He/she will also work closely with designers, developers, and physicists to understand what is needed and provide the appropriate support to help the team accomplish assigned goals and tasks.
The ideal candidate will have solid skills with software tools and data inputs typically used in the design of microelectronics ASICs and strong experience supporting successful design efforts that culminate in tapeouts.
Digital CAD Tool/Flow/Methodology Developer Responsibilities include:
- Define and lead the development of innovative and effective RQL (Reciprocal Quantum Logic) design flows
- Collaborate with circuit designers and PDK engineers on library development and modeling to support the tool/flow
- Understand and guide the use of configuration management
- Provide design/CAD team strong scripting capabilities in SKILL, PERL, Ocean, Linux Shell, etc.
- Interface with CAD tool vendors to prove out releases and flows, solve bugs, improve usability, etc.
- Oversee the Installation of new software and software updates and perform flow signoff
- A Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with at least 2 years of relevant experience (or technical MS or PhD with 0 years)
- The ability to obtain and maintain a DOD security clearance which requires U.S. Citizenship
- Solid knowledge of the Cadence Virtuoso environment AND DRC/LVS/PEX within Cadence Assura or Mentor Graphics Calibre
- A working knowledge of the ASIC design flow from RTL to GDSII
- Familiarity with EDA standard formats used in cell/library development and modeling LEF (library exchange format), DEF (design exchange format), Liberty (timing model), OA (OpenAccess), SDC (Synopsys Design Constraints)
- Proficiency with current ASIC tools
- Demonstrated ability to script capabilities within a CAD environment (Skill, Perl, Tcl, Python)
- Knowledge of configuration control and directory management within a CAD environment
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