Integrated Circuit Virtuoso Engineer 3

Northrop Grumman, Mission Systems is seeking a candidate for the position of Integrated Circuit Virtuoso Layout Engineer 4 in the Electrical Design Technology (EDT) organization. The position is located at the Advanced Technology Lab (ATL) in Linthicum, MD where we design, manufacture, and test semiconductor products for internal and commercial production as well as emerging programs. The ideal candidate will have solid layout skills in Cadence Virtuoso and strong experience scripting repetitive needs in SKILL, PERL, Linux Shell, etc. The development nature of our foundry activities will provide a willing candidate the opportunity to develop into an integral member of the foundry organization.

Responsibilities include:

  • Generate Virtuoso layouts for Process Control Monitor (PCM) structures with guidance from process development engineers
  • Generate Virtuoso layouts for alignment marks with guidance from photo lithography engineers
  • Generate Virtuoso layouts for physical measurement structures with guidance from process development and photo lithography engineers
  • Generate Virtuoso schematics and layouts for test circuits that are sub-circuits of larger integrated circuits with guidance from design engineers
  • Participate in reticle composition and tape out support activities
  • Aid in troubleshooting related to all of the above
  • Create and document flows for future re-use and quality control

Basic Qualifications:
  • This job requires a Bachelor's degree (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with an MS and 0 years with a PhD). Relevant Masters level coursework or projects will be considered in lieu of relevant work experience.
  • Experience using Cadence tools to layout Integrated Circuits, perform Mask Layout, Full Custom Layout and/or draw structures used typically in a Microelectronics Foundry environment
  • Experience using Cadence Schematic Editor tools to create circuits
  • Demonstrated ability to script capabilities within the Cadence environment using one of several compatible scripting languages
  • Knowledge of Cadence XL/GXL capabilities that enhance layout task efficiency
  • Solid knowledge of the Cadence environment AND DRC/LVS/PEX within Cadence DIVA, Assura, PVS or Mentor Graphics Calibre
  • Solid interpersonal and team skills for cross-functional collaboration. High attention to detail and ability to self-check work outputs
Preferred Qualifications:
  • Knowledge of semiconductor device physics, process development, analog/mixed signal integrated circuit design, manufacturing and testing
  • Experience utilizing the spectre simulator to verify models match measurements
  • Experience laying out digital standard cells and memory elements or characterizing standard cells and memories
  • Experience with Process Design Kit (PDK) Development (techfiles, verification rulefiles, p-cells)
  • Proficiency with Cadence Assura DRC/LVS/PEX or the Mentor Graphics Calibre suite of verification tools

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit . U.S. Citizenship is required for most positions.${descr2}${descr3}

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