Engineer Circuit Design 2
Northrop Grumman San Diego calling ! Our Advanced Digital Design organization creates the next generation of communications and signal processing systems, and will take ideas from concept to working systems aboard the world's most advanced platforms right here in always-sunny San Diego. We design in our campus of labs and on-site advanced manufacturing just minutes from the beach and everything for which southern California is famous. It's work that matters and a career that can takes you places.
We seek degreed engineers with at least 3 years hands-on experience in board level design & layout, high speed digital circuit implementation using FPGAs, and advanced circuit board technology. Experience includes understanding of schematic capture, prototype build, fabrication and production test. Hands on understand of troubleshooting, determination of root cause, definition of corrective action and implementation of solutions. Previous experience with very high speed interfaces, ultra fine-pitch components and advanced manufacturing considered essential. Understanding of affordability and production factors in state-of-the-art manufacture and test. Experience includes history of collaboration with other engineers and cross-functional teams in developing high-speed digital hardware for signal processing.
Typical Minimum Education / Experience for a level 2: 3 years with a Bachelor of Science in Electrical Engineering (BSEE) or related field of study, 0 years with a Masters.
BSEE degree from a regionally-accredited college or university. Minimum of 3 years of relevant experience in board level high speed digital circuit implementation and proven ability to perform prototype design, build and production test.
"Additional technical skills should include Xilinx Vivado or Altera Quartus-II and hands-on experience with the either Xilinx Zynq SOCs or the equivalent from Altera, knowledge of PCIe Gen2 or Gen3, the AXI bus protocol, and hands-on debug and integration of large-scale FPGAs. Use of Vivado-specific JTAG debug capabilities such as ILAs, JTAG-based IP or equivalent preferred. Regression simulation experience with Mentor Graphics ModelSim or QuestaSim to replicate observed corner-cases from the lab to resolve integration issues strongly encouraged.
Exposure to concepts related to the OSI 7 Layer model particularly Layers 1-4 helpful – receiving, transmitting, and parsing variable-length packets of data, operating on packet payloads, and encapsulating waveforms to transform packet content helpful. Direct experience with one or more PHY standards (Ethernet, PCIe, RapidIO, or others) also desired."
Expertise in multilayer board design, signal integrity, and communication systems.
Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.
Meet Some of Northrop Grumman's Employees
Jacqueline operates on power electronics for Northrop Grumman’s space application projects. She meets with engineering groups, chats with customers, and works on circuit analysis.
Back to top