Digital Integrated Circuit Designer (level 3/4)

Did you know that Northrop Grumman’s Advanced Technology Lab is developing a new family of superconducting digital logic known as Reciprocal Quantum Logic (RQL)? On a gate for gate basis, RQL consumes five orders of magnitude less power than CMOS while running at significantly higher clock speeds. Having demonstrated its performance with basic circuits, we are now developing processors, memories, and larger systems.

We are seeking a front-end ASIC Digital Design Engineer (level 3 or 4) for design, implementation, and verification of full-custom digital and mixed signal Superconducting Circuits. He/she must be proficient in Verilog, System Verilog or VHDL RTL coding, writing functional test benches and have a thorough understanding of synchronous digital design concepts.

The Digital Design Engineer must be able to create a functional verification plan based on the requirements of the circuit; be able to generate manufacturing test vectors and manufacturing test plans; be knowledgeable in synthesis, SDC constraints, formal verification, and static timing; and be able to interface with place and route engineers for floor-planning, clock constraints, and timing closure. Knowledge of scan insertion, ATPG, Automated Place and Route, and physical verification is a plus.

The ideal candidate must have strong written and oral communication skills and be comfortable working in a research environment with shifting priorities and requirements. ACandT

This position may be filled as a level 3 or a level 4 based on the qualifications below.

This position may be filled as a level 3 or a level 4 based on the qualifications below.

Basic Qualifications for a level 3:

  • Bachelor’s degree in a technical area (BSEE or other Engineering discipline preferred)
  • 5 years of relevant experience (3 years with technical MS or 0 with technical PhD)
  • Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
  • Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
  • Proficiency with current ASIC design tools for all phases described above
  • *Simulation – Mentor ModelSim, Cadence Incisive or Synopsys VCS
  • *Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
  • *Static Timing – Synopsys Primetime or Cadence Tempus

Basic Qualifications for a level 4:

  • Bachelor’s degree in a technical area (BSEE or other Engineering discipline preferred)
  • 9 years of relevant experience (7 years with technical MS or 4 with technical PhD)
  • Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
  • Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
  • Proficiency with current ASIC design tools for all phases described above
  • *Simulation – Mentor ModelSim, Cadence Incisive or Synopsys VCS
  • *Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
  • *Static Timing – Synopsys Primetime or Cadence Tempus

Preferred Qualifications:

  • Advanced Degree – either MS or PhD
  • Current security clearance or eligibility
  • Experience with chip level integration and ASIC chip lead
  • Strong design automation skills
  • Experience in CAD design network, tool configuration, and data management
  • Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre
  • Familiarity with revision control and EDA standard formats used in cell/library development and modeling – Liberty (timing model), SDC (Synopsys Design Constraints)

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.

ACandT


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