Digital Integrated Circuit Designer 5
Did you know that Northrop Grumman's Advanced Technology Lab is developing a new family of superconducting digital logic known as Reciprocal Quantum Logic (RQL)? On a gate for gate basis, RQL consumes five orders of magnitude less power than CMOS while running at significantly higher clock speeds. Having demonstrated its performance with basic circuits, we are now developing processors, memories, and larger systems.
We are seeking a Digital Design Engineer for design, implementation, and verification of full-custom digital and mixed signal Superconducting Circuits. The ideal candidate will help drive to a common set of designs and design procedures across multiple Superconducting programs. He/she must be proficient in Verilog, System Verilog, or VHDL RTL coding and writing functional test benches; and have a thorough understanding of synchronous digital design concepts.
The Digital Design Engineer must be able to create a functional verification plan based on the requirements of the circuit; be able to generate manufacturing test vectors and manufacturing test plans; and be knowledgeable in synthesis, SDC constraints, formal verification, static timing, floorplanning, automated place and route, clocktree insertion and timing closure. Knowledge of scan insertion and ATPG is a plus.
The ideal candidate must have strong written and oral communication skills and be comfortable working in a research environment with shifting priorities and requirements. ACandT
- Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred)
- 14 years of relevant experience (12 years with technical MS or 9 with technical PhD)
- Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of ASIC design
- Working knowledge of the entire ASIC design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification)
- Proficiency with current ASIC design tools for all phases described above
- *Simulation – Mentor ModelSim, Cadence Incisive or Synopsys VCS
- *Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
- *Static Timing – Synopsys Primetime or Cadence Tempus
- *Place and Route – Cadence Encounter or Innovus or Synopsys ICC
- Advanced Degree - either MS or PhD
- Current security clearance or eligibility
- Strong design automation skills
- Experience in CAD design network, tool configuration, and data management
- Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre
- Familiarity with revision control and EDA standard formats used in cell/library development and modeling – Liberty (timing model), SDC (Synopsys Design Constraints)
Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.
Meet Some of Northrop Grumman's Employees
Jacqueline operates on power electronics for Northrop Grumman’s space application projects. She meets with engineering groups, chats with customers, and works on circuit analysis.
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