CAD Tool and Methodology Developer 3/4

Northrop Grumman Mission Systems (NGMS) is seeking CAD Tool and Methodology Developer(s) for our Advanced Concepts & Technologies (AC&T) Organization. The position is located at the Advanced Technology Lab (ATL) – situated outside of Baltimore, MD – where we design, manufacture, and test semiconductor products for internal and commercial production as well as emerging programs.

The CAD Tool and Methodology Developer will lead the creation of new design flows and design capabilities by leveraging existing commercial tools, harnessing custom engineered scripts, and working with EDA vendors and internal developers on custom tools. He/she will also work closely with designers, developers, and physicists to understand what is needed and provide the appropriate support to help the team achieve program goals.

The ideal candidate will have solid skills with software tools and data inputs typically used in the design of microelectronics ASICs and strong experience supporting successful design efforts that culminate in tapeouts.

Responsibilities include:

  • Define and lead the development of innovative and effective RQL (Reciprocal Quantum Logic) tools and design flows
  • Collaborate with circuit designers and PDK engineers on library development and modeling to support the defined tool/flow
  • Collaborate with senior designers, system architects, and principal investigators to prioritize features and enhancements and maintain tool roadmap
  • Understand and guide the use of configuration management to support multiple concurrent processes, projects, and development efforts
  • Interface with tool vendors and other developers to prove out releases and flows, solve bugs, and improve usability
  • Validate CAD software and software updates and execute flow signoff to meet program needs
  • Peer review work of other team members
  • Create & maintain tool and methodology specifications and documentation ACandT

This requisition may be filled at either a level 3 or a level 4 based on the qualifications below.

Basic Qualifications for a level 3:

  • The ability to obtain and maintain a Department of Defense security clearance. (U.S. Citizenship is a pre-requisite of this).
  • A Bachelor’s degree in a technical area with at least 5 years of related ASIC project experience (OR a Master’s degree in a technical area with at least 3 years of ASIC project work experience OR a PhD with at least 1 year of ASIC project work experience)
  • Proficiency with current digital ASIC design tools from RTL to GDSII including at least 4 of the following: Synthesis, Formal Verification, Static Timing, Floor planning, Placement, Routing, and/or Physical Verification
  • Familiarity with EDA standard formats used in cell/library development and modeling including all of the following: LEF (library exchange format), DEF (design exchange format), Liberty (timing model), OA (OpenAccess), SDC (Synopsys Design Constraints)
  • Demonstrated ability to script/automate within a CAD environment using one or more of: Skill, Perl, Tcl, Python, bash
  • Knowledge of configuration control and directory management within a CAD environment
  • Excellent written and verbal communication skills for tool specifications, reviews, and interaction with other teams

Basic Qualifications for a level 4:

  • The ability to obtain and maintain a Department of Defense security clearance. (U.S. Citizenship is a pre-requisite of this).
  • A Bachelor’s degree in a technical area with at least 9 years of related ASIC project experience (OR a Master’s degree in a technical area with at least 7 years of ASIC project work experience OR a PhD with at least 4 year of ASIC project work experience)
  • Proficiency with current digital ASIC design tools from RTL to GDSII including at least 4 of the following: Synthesis, Formal Verification, Static Timing, Floor planning, Placement, Routing, and/or Physical Verification
  • Familiarity with EDA standard formats used in cell/library development and modeling including all of the following: LEF (library exchange format), DEF (design exchange format), Liberty (timing model), OA (OpenAccess), SDC (Synopsys Design Constraints)
  • Demonstrated ability to script/automate within a CAD environment using one or more of: Skill, Perl, Tcl, Python, bash
  • Knowledge of configuration control and directory management within a CAD environment
  • Excellent written and verbal communication skills for tool specifications, reviews, and interaction with other teams

Preferred Qualifications:

  • Active Secret Clearance (or higher)
  • A Bachelor’s degree in Electrical Engineering or other engineering discipline is preferred)
  • 10 years of ASIC project experience including at least 5 of those years in an ASIC lead or flow lead position.
  • Methodology development and flow deployment, user support
  • Prior experience as an application engineer at an EDA vendor
  • Current design closure experience with Cadence tools: Genus, Innovus, Tempus, Conformal, Nanoroute
  • Project management or software development lead experience
  • Experience managing change in a highly dynamic research & development environment
  • Familiarity with cell design and layout using Virtuoso

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.

ACandT

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