- Bengaluru, India
- In this position, the candidate will be responsible for the following . - - Qualify complex Audio IP ( consisting of multiple power domains/partitions/clock domians) on multiple process nodes, ensuring timing/power/performance requirements are met, along with all design tool quality requirements. - Debug execution and design issues at every step. - Identify and fix synthesis elaboration issues. - Identify timing closure issues, suggest possible solutions. - Work with designers on providing correct timing/design/power constraints. - Identify design issues related to clock-gating, optimization methods, library selection, etc.
• Qualification : - Master of Science (or a Master of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than ten years of relevant industry experience. - Experience : Relevant ASIC design experience - Expertise in verilog and system verilog based logic design - Experience with IP Design Tool Flow methodologies - Strong experience in synthesis and timing closure - Experience in Industry standard tools like Spyglass Lint, Spyglass CDC, DC, LEC - Experience in DFT tools, Simulation tools, VC LP, Fishtail, Power artist - Expert level knowledge of Unix, Perl, Python, Design Compiler, Conformal. - Good understanding of Front-End methodologies - Looking for highly motivated individuals who has passion to solve TFM problems for IPs - Ability to work with EDA vendors to solve Design tool issues.
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
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IN Experienced Hire JR0149596 Bangalore
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