System Validation Engineer
- Santa Clara, CA
In this role responsibilities include, although not limited to:
- Creates, defines and develops system validation environment and test suites
- Uses and applies emulation and platform level tools and techniques to ensure performance to spec
- Responsible for the development of methodologies, execution of validation plans, and debug of failures
- Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving Post-silicon test content and providing feedback for future ondie debug features
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience -OR- a Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience:
- Microprocessor validation
- Knowledge of Memory Controller
- CPU micro-architecture and/or high-speed bus protocol
- Debug skills and willigness to drive resolution of critical issues
- CPU core, Virtualization, Memory, PCIE, UPI, Power Management, RAS, Security, and/or Coherency
- Intel architecture and/or Intel chipset experience
- Logic or Protocol Analyzer equipment
- Python Scripting Experience
Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.
US, Oregon, Hillsboro;US, Texas, Austin
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
US Experienced Hire JR0142084 Santa Clara
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