Job Description
Job Description: MIG Malaysia is seeking Staff Verification Engineer to join our talented and vibrant DDR team.You will have the opportunity to directly involve in developing the latest generation of DDR PHY IP forSOC application on Intel leading process node.In this position, your responsibilities will include but not be limited to: Define high performance and low power DDR I/O micro-architecture specification or pre-siliconverification for the next generation computing memory architecture. Develop pre-silicon verification OVM/UVM based environment/test-bench and test sequences. Develop BFMs to interface with the IP with the capability of monitoring transaction and checking protocol. Define verification strategies, methodologies and write complete test plans. Develop test cases, assertions and functional coverage using System Verilog. Setup and run GLS to verify the asynchronous and multi-cycle paths. Debug test failures, and implement corrective measures for the failing conditions. Analyze and drive functional coverage. Develop automated tools or scripts for pre-silicon verification efficiency improvement. Collaborate with SOC/Sub-system on IP integration issues. Collaborate closely with micro-architects and logic/analog designers. The successful candidate requires a strong technical background in micro-architecture design,logic and verification methodology. They need to be someone who is passionate about working in a dynamic environment where the expectation is to contribute in any activity that makes the business successful. Candidate must have strong communication skills verbal and written, teamwork skills, be a self starter,and have the capability of managing a dynamic work environment.
Qualifications

Qualifications: Candidate must have a Bachelor, Master or PhD Degree in Computer Engineering, Electrical Engineering, Computer Science or related field. Candidate will have 10 years of hands-on experience with Logic Design and/or Pre-Silicon Verification Candidate must possess strong fundamentals on the following area: o Good understanding in SV, OVM/UVM and verification methodologies o Experience in using verification tools such as VCS, DVE, Verdi, etc. o Have strong fundamental knowledge in JEDEC specification, DDR architecture (LP)DDR 4/5, Denali, and have extensive coding experience that includes logic behavioral modelling SV coding. o Good understanding in High Speed I/O Design and Mixed signal design. Possess strong fundamental knowledge of HW description language (Verilog and assertion coding) and logic simulation. Experience in IP integration is an added advantage. o Have experience in power aware design, UPF & multi-power domain checks. o Strong in problem solving, debugging various simulation failures, and formal verification. o Strong written and oral communication skill, able to communicate well with counterparts and key stakeholders including cross-site partners. o Experience with post silicon DDR debug and IO training is an added advantage.
Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

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