Sr. Structural Design Engineer
The Datacenter Graphics Products Group within the Graphics and Throughput Computing Hardware Engineering (GTCHE) organization, which is part of the IAGS (Intel Architecture, Graphics and Software) Supergroup, is responsible for the development of discrete Graphics and AI SoCs for Datacenter applications. We are looking for a Sr. Structural Design Engineer with scope of work encompassing synthesis, scan, floor planning, auto place and route, clock tree synthesis, equivalency verification, static timing analysis, reliability and layout closure.
• BE/B.Tech/ME/M.Tech/MS in Electrical and/or Electronics Engineering with 14 years of relevant industry experience including a minimum of 7 years in VLSI design with expertise in RTL-to-GDSII flow, floor planning, Clock tree synthesis and block-level/chip-level signoff.
• Needs to be familiar with all aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning and hard IP integration. Experience solving SoC issues such as ESD strategies, mixed signal block integration, and package interactions. Familiar with hierarchical design approach, top-down design, area budgeting and physical verification convergence. Must have experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain. A detailed understanding of database management issues will be required.
• Expertise using leading-edge EDA tools Synopsys, Cadence or Mentor Graphics from a CAD tool perspective, experience with floor-planning tools, P&R flows and physical design verification flows is required.
• Make, Perl and Python expertise is nice to have.
• Motivation to drive an exciting project. Very effective team player. Excellent verbal and written communication skills
• Preferred Qualifications:
o Experience in custom / data-path implementation is highly desirable. Should be be able to specify and drive IP requirements in the physical domain
o Ability to plan, execute, course correct and optimize blocks and SoC level implementations. Ability to provide mentorship and guidance to junior engineers.
Inside this Business Group
The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.
IN JR0106600 Hyderabad
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