Looking for a senior pre-silicon verification engineer who can define, strategize and execute with quality for Intel's IP development group. The candidate should be able to develop validation plans, build validation environment, create test plans and drive IP validation until signoff, using industry standard tools. Should have good experience and expertise on creating coverage plans that ensure high quality validation. Should be able to communicate across various domains - architecture, design, post-silicon validation teams across various Intel sites worldwide on technical details, project status & plans, with project leads and upper management.
The candidate should have the following: Proven expertise in IP product development and playing a lead role in design/validation. Expertise in validating complex IPs. In-depth knowledge of System Verilog and extensive experience in creating validation environment in OVM/UVM from scratch. Sound understanding of functional verification strategies, directed/random testing and debug is a must. Should have experience in Gate Level verification with SDFs. Experience with AMS validation for complex IPs is a big plus.
Ability to work as an individual as part of a high performing team as well as experience in leading pre-silicon validation teams from planning to delivery. Experience with bring-up/debug in the lab is also a plus. Excellent written and verbal communication skills.
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
IN JR0159600 Bangalore IP Engineering Group (IPG)