We are looking for SoC Design Engineers with Design Automation roles. Your responsibilities in this highly visible role will include but not be limited to: -
- Develop, support and drive project execution formal verification flows and methodology for cell-based and/or transistor-based designs.
- Drive solutions to perform formal verification, logic equivalence checking (LEC) using both external Engineering Design Automation (EDA) tools and internal CAD tools for back-end design work (design construction, power estimation and optimization, formal verification and RTL ECO)
- Partner with CPU design team engineers to highlight issues, debug complex problems and develop innovative solutions for analysis debug, flow scripts and signoff
- Creates flows/scripts to analyze, test and improve design methodologies
- Develops custom optimized solutions to address design requirements for latest technology nodes
- Provide technical direction by identifying gaps in current EDA solutions and drive enhancements through vendors
- Contribute to the development of multidimensional designs involving the layout of complex integrated circuits.
- Expand and standardize design methodologies, especially those related to synthesis, formal verification, activity annotation for power estimation, and ECOs.
- Documenting and helping with guidelines/specs
The ideal candidate should exhibit the following behavioral traits:
- Inter-personal, clear communication and teamwork skills.
- You need to possess a can-do attitude, are driven by research, problem-solving, and thrive on challenges.
- Self-motivator with strong problem solving skills
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must have a Bachelors in Electrical and Computer Engineering or related field and 3+ years of experience with: - OR - a Masters degree in Electrical/Computer Engineering or related field and 1+ years of experience with:
- Design principles and techniques in VLSI back-end design, custom-circuit (transistor) design and/or memory design
- UNIX/Linux environments and Perl/Tcl/Shell/Python scripting
- Familiarity with RTL Verilog language
- Familiarity with backend design EDA tools Synopsys, Cadence and/or Mentor Graphics
1+ year of experience with:
- Design Automation for CPUs or SOCs, including formal verification/logic equivalence checking of gate level and/or transistor level designs (RLS, SPICE) in advanced CMOS processes
- Industry standard Engineering Design Automation (EDA) VLSI tools from Synopsys/Cadence in one of more of the following: Timing/Power optimization, ECO, Static Timing Analysis, SPICE circuit simulation, statistical variation analysis, noise, cross-talk, OCV and/or ERC flows
- Machine-learning methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement
- Synopsys/Cadence Tcl coding
Inside this Business Group
The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
US College Grad JR0157220 Austin Devices Development Group (DDG)