SOC Backend Engineer for Full-Chip Timing
The position is for SOC BE design engineer (focusing on full-chip integration and STA) in the integration team which is part of the high-end CPU design group.
You will be part of the team delivering Intel's leading client CPU products, specifically working on complex SOCs with many clocks and different design IPs.
You will be familiar with design integration and static timing analysis methods, tools and flows used at Intel. You will work closely with worldwide CPU design teams on BE design integration & convergence, including IP integration. You will be familiar with design environment, flow, tools, methodologies and optimization methods used at Intel.
You will be exposed to leading technologies used in CPU design at Intel.
This position requires wide expertise and understanding of Back End design flows (RTL2GDS).
This is career development opportunity for Back End design engineers who wish to expand their horizons to Full-Chip level design convergence.
3-5 years of Back End/ Physical design experience, hands-on experience in RTL2GDS flows.
Ability to drive others, you will work in a complex environment with many stakeholders.
Must hold at least a BSc. in Electrical Engineering or Computer Engineering.
Experience in static timing analysis and full-chip integration in SOC design
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
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