Senior Staff Analog Circuit Design Engineer
MIG MYS is seeking senior mixed-signal design engineers to join our talented and vibrant team. You will be directly involved in delivering next-generation LPDDR5/DDR5 PHY designs for SOC application on Intel leading process node.
Key Responsibilities include but not limited to:
- Design and development of mixed-signal circuits such as High Speed Transmitters and Receivers, equalizers, DLL, clocking distribution, on die voltage regulators and references blocks.
- Own design verification plans covering functional, performance and reliability meeting high volume productization requirement.
- Participate in circuit design review and work with Mask Designers on layout implementation and reviews
- Collaborate with design engineers of other disciple on integration of the analog circuit to the DDR PHY
- Mentoring of junior engineer
Qualifications Preferred Qualification:
- Proven track record on design of high speed analog and mixed-signal design, architecture, system and integration aspects for DDR PHYs
- Good Understanding of to LPDDR/DDR JEDEC specifications and related DDR Protocols
- Good understanding of design for yield and exposure to production challenges in latest technology process node
- Experience with industry standard tools for Analog design such as Cadence ADE, Spectre, AMS verification, FEV, StarRC etc..
- Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation.
- Strong written and oral communication skills
- BSEE with 10 years relevant experience or Master's with 7 years relevant experience required. Education Focus should include integrated circuit design and analog design.
Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.
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