Senior Soft IP Design Engineer
- George Town, Malaysia
This position will work within an R&D team which develops soft IP in RTL and associated collaterals for Intel latest chipset and SOC products. The responsibilities will include (but not limited to):
- Performs IP level logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries and functional units for inclusion in sub-system and downstream SoC or chipset designs.
- Participates in the development of Architecture and Microarchitecture specifications for IP.
- Advises IP sub-system integration in supporting SoC customers and represents the Soft IP team.
The applicant should have a Bachelor degree in (Electrical & Electronics or Computer or equivalent) Engineering or higher, and at least about 7 years of experience in RTL design and verification.
- Familiarity or experience in RTL design with Verilog and/or VHDL is required.
- Familiarity or experience with RTL verification and timing analysis/closure is required.
- Knowledge of high-speed serial system interfaces (such as PCI Express or USB) is a strong plus.
- Familiarity with Perl, C and shell scripts is a plus.
- Strong skills in communication, initiative, promote innovation and collaboration.
- Highly motivated to learn and adapt to fast-evolving technologies and environments.
Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.
MY Experienced Hire JR0140050 Penang
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