Senior Post-Si Validation Technical Leader
- Bengaluru, India
"This is a senior technical leadership role in a highly dynamic organization working on industry leading data center SoC products. This role is responsible to drive Post-Si Validation driving validation architecture, drive the teams to develop high quality Post-si test plans/content development and deliver highest quality of coverage meeting the production quality expectations for the SoC. Uses and applies emulation and platform level tools and techniques to ensure functional quality and performance to spec. Responsible for the development of methodologies, execution of validation plans, and debug of complex failures. Requires broad understanding of multiple system areas and requires interfaces with SoC Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and design for validation capabilities. Will technically represent validation in various senior management reviews and be accountable for making technical decisions for the team and program. Provides guidance/mentor ship different validation leads/engineers and plays key role in strengthening technical capabilities in the team
• Bachelor's/Master's in Hardware Engineering or Electrical/Electronic Engineering or Computer Engineering or Computer Science with 15 years of experience
• Candidate must have high degree of Hardware architecture/ microarchitecture experience in CPU/SoC/Chipset/and one of the subsystems areas given below
• Strong knowledge and skills of Intel IA (IA32 architecture with uArch debug knowledge of Intel's Core and Uncore or equivalent architecture.)
• Deep understanding of Cache coherency, virtualization, system level memory and Power Management architecture knowledge is a must
• Hands on work in finding bugs in post silicon through fine tuned content in the domain of coherency and concurrency [cross products with PM, PCIe, ethernet etc]
• Good understanding of memory Controller / DDR (2/3/4) memory architecture and debug
• Hands-On experience of complex SoC sightings and exposure to running cross-site TFs
• Knowledge on Debug Tools for JTAG, on chip trace features and ability to debug via OSC/LAs etc; Usage of any Post-Si debug tools (e.g., logic analyzers, oscilloscopes, things like ChipScope on FPGA's, etc.), usage of different Analyzers/exercisers (PCIe etc.) o Familiarity with FW (embedded uC) debug - ARC or Extensa LX-series uC preferred
o Knowledge of ARM PM concepts (e.g., P/Q-channel) is a plus
• Pre-silicon Design / Validation knowledge is a value add.
• Excellent written and oral communications and experience of working in a cross functional and cross site team environment are essential, combined with ability to handle high level technical ambiguity.
Inside this Business Group
The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....
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