Senior Architect, Memory Reference Code
- Austin, TX
We write the firmware that trains the memory that enables our customers to provide the bandwidth required to run the workloads that make people's lives better.
Right now we are redesigning our firmware so that we can support the industry needs with faster time to market, higher speeds and faster training times.
We need people passionate about software quality, innovation and doing the work right.
As a Senior Architect you will use your experience with memory technologies to align our requirements with our code, but you will not only write specifications; we expect that you will teach the team and we expect, most importantly, that you will show the team how to write good software.
All of our development has moved into pre-silicon, so we need to work closely with silicon design and validation teams to test our firmware before PO. This is a key focus for us, so experience in any part of silicon design and pre-silicon validation will be helpful.
Once we get silicon, either the final product or a test chip, we work directly with analog validation partners to verify all our training algorithms. A deep knowledge of the Jedec specifications and how all the training steps work is required so that you can contribute to the collaborative debug. Working as a team is critical to success, as we work systematically through the problems.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job.
- Bachelor's in Electrical Engineering, Computer Engineering or related equivalent with 6+ years of work experience or Master's degree in Electrical Engineering, Computer Engineering or related field with 4+ years of work experience.
- 1+ year's of experience of memory controller or memory PHY and DDR memory protocols.
- 3+ year's of experience with pre-silicon simulation verification or post-silicon memory subsystem verification.
- 4+ year's of experience with C programming.
- Python programming experience.
- UEFI BIOS development experience.
- Proven experience debug methodology and skills.
Inside this Business Group
Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level-not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.
US, Massachusetts, Hudson;US, Oregon, Hillsboro
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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