Runset QA Engineer
- Bangalore, India
Physical Design Verification Runset Quality Checks is the primary job function. Debug the DRC/LVS rule deck failures during regressions and document the failures to the development team. Developing the layout patterns to check every design rule in the redbook/design manual and integrate them into the QA regression suite is the work nature on daily basis. Automation of central regression system and maintain/manage test bench is the crucial job function
B Tech 6 yr's experience or MS 4 yrs' in Electrical / Electronic engineering is required. Experience with ICV and Calibre Layout verification runsets is a must. Experience working on 7nm or lower process nodes desired. Strong automation/scripting skills are required (Tcl/Python/Perl). Desire to grow in the physical verification design career path is preferred.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
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IN Experienced Hire JR0140936 Bangalore
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