Pre-Silicon verification Engineer for ACES

Job Description
ACES department (Architecture, Circuits, Ethernet and SerDes IP's) is looking for Pre-Silicon verification Engineer.
About us :
ACES develops and delivers PLL's and all High Speed networking and communication building blocks (as Ethernet PHY, PCIE, USB-TypeC, DP/HDMI) to all Intel devices (Client and Servers CPU's / Chipset / Controllers). Team delivers state of the art technologies as 112G and higher Ethernet PHY in Intel process (14nm/10nm/7nm).
We're looking for engineers for Ethernet PHY pre-silicon verification team located in Jerusalem.
About you :
In this role you will deal with all the verification phases along the project, from learning the specs and the design, defining environment and test plan, implementing the environment and run & debug simulations.
The team is also taking part in the post-silicon validation effort in the lab.



  • BSc or MSc in Electrical Engineering or Software Engineering
  • At least 5 years of experience in Pre SI validation
  • Creativity and team work
  • Knowledge in System-Verilog - advantage.
  • Knowledge in OVM/UVM methodology - advantage.
  • Knowledge in digital PHY- advantage.

IMPORTANT: Please be informed that Intel is proactively trying to find candidates for a Verification Engineer position and that this position may not be available at this time.

Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

Other Locations
Israel, Petah-Tikva;

IL JR0096111 Jerusalem

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