Pre-si Solution and Validation Senior Engineer
This engineer position is part of the Malaysia Design Center (MDC) under Intel Validation Engineering (iVE) organization in Malaysia. Responsibility includes developing capabilities in Emulation/FPGA environment, and validation of Intel silicon in pre-silicon and post-silicon, including test plan, test content development, execution of validation test and debugging system failure. The focus of this team will be Intel silicon on data centre and discrete graphics products, covering features in system security, memory, power management, and high speed IO. The successful candidate must be able to work effectively with cross functional teams such as Silicon Design, and FW/SW development team. Requires broad understanding of multiple system architecture, silicon design/validation methodologies, and Emulation/FPGA technologies.
Bachelors or Master Degree in Computer Science/Electrical/Electronic Engineering with 7 to 10 years of technical experience. Knowledge in C/C , SystemVerilog, and Python is desirable. Intel Architecture knowledge of system security, memory, power management and high speed IO is a plus. Good understanding of silicon design, system architecture, and FW/SW flow. Experience in silicon debug, RTL validation, SW validation, or Power/Perf validation is a plus. Experience in Emulation, Virtual Platform, Altera/Xilinx/Synopsys/Mentor/Cadence Tools Flow, HAPS is a plus. Should have strong communication, analytical skill and a good team player.
Inside this Business Group
The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.
MY Experienced Hire JR0153092 Kulim Intel Validation Engineering
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