Post-silicon Senior Design Engineer
- Haifa, Israel
Intel Israel has an opening for a Senior Design Engineer focused on post-Silicon product design enabling and optimization. This position is in Intel's "center of excellence" for Silicon design debug supporting Client products. This team resolves product quality and performance issues blocking products from meeting production requirements with a combination of design and manufacturing problem solving expertise, leveraging state of the art methodologies & tools.
This team is a critical ingredient to Intel's strategy of enabling strong design debug support for our entire product portfolio and scaling it going forward.
BS/MS Engineering (EE, CompE).
Previous experience in semiconductor circuit design.
Strong verbal and written communication skills (English).
Hands-on, self-motivated problem solver.
Knowledge of DFT (Design for Test), previous experience in Array and Scan could be an advantage
- Scan and Array infrastructure good knowledge
- Scan and Array insertion with Mentor/Synopsys tools
- Scan and Array Pre/Post Si validation and Si enabling
- Debug of Si issues using Scan/Array/JTAG/TAP
- Debug yield loss by using SCAN and Array diagnosis
Digital circuit design methodology.
Design structural & functional diagnosis tools & methods.
Knowledge of post silicon validation concepts/methods including:
High Volume Manufacturing (HVM).
Test flows including die level and package level testing.
Test stimulus & coverage approaches.
Inside this Business Group
Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.
IL Experienced Hire JR0142873 Haifa
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