Platform Targeting Leader & Manager
Responsible for leading a team of device, cell and block-level PPA (power, performance & area) & EoU (ease of use) modeling and targeting prediction experts focused on competitive foundries, who can provide detailed technical analysis and input to the PPA / EoU validation team, competitive analysis team as well as the process technology development team on what process technology changes and features are being potentially implemented by the competitive foundries to achieve their best-in-class PPA & EoU targets for n, n 1 and n 2 technologies.
The Targeting Leader & Manager plays a key role by assembling and bringing together a diverse set of domain experts to collect, assemble & triangulate competitive PPA & EoU data (what), interpreting its findings (how & why) and employing modeling and simulation techniques to fill in gaps and project a more comprehensive picture of the competitive offerings of the foundries in a similar time frame, for the same market segment of interest as competing Intel products.
The key focus for this Targeting Team, led by the Targeting Leader & Manager is as follows:
- Establish methodology for CAGR-based projections for future Foundry nodes including mock process flows
- Generate device models based on various external inputs and reflect parasitics of physical layout from multiple cell types
- Generate Foundry Market targets for 3yr to 5yr horizon based on external inputs and market sensing; maintain 1-2yr targets and improve them when additional data is available Calibrate market targets through DTCO engagements with IP suppliers, EDA vendors and external customer engagements
- Build and maintain a common, referenced and change-controlled market Foundry data base, so that we're all using the same market data across Intel, including P2CA
To focus on the key areas described above, the Targeting Leader & Manager's responsibilities include:
- Assemble & manage a team of technical platform domain experts (in libraries, memories, foundational IOs, place & route, Performance / Power / Area (PPA) and Ease-of-Use (EoU) forecasting & analysis) to engage in market data collection & analysis initiatives, DTCO (design-technology co-optimization) and technology platform specification initiatives that enable technology platform definition that's driven by market-based PPA and EoU competitive technical targets
- Develop PPA & EoU forecasting methodologies, models and tools, so that we can improve our ability to reasonably and accurately predict where the competition will be in future process nodes and technology platforms.
- Perform feature and / or landing zone trade off analysis with transistor, metal stack, library, memory and analog architects and process technology engineers to ensure that we fully comprehend how the competitive foundries are enabling best-in-class process technology & product performance.
- Participate in block-level and foundational IP level benchmarking exercises to replicate and predict where the foundry competition is at and will be in the future, so that we can better understand the feature and / or landing zone tradeoffs that are being considered across the industry.
- Jointly with the Competitive Analysis Team, build and maintain a common, referenced and change-controlled competitive data and competitive analysis data base, so that we're all using the same competitive data and competitive analysis across Intel.
- Interact with fellow DTCO partners and external customers to ensure that we're aligned on market-based targets that can used during the DTCO engagement to make key technology feature decisions / trade-offs and help the organization understand the implications and impact of these decisions on platform targets.
To ensure effectiveness and significant impact, the Targeting Leader & Manager must possess the following capabilities:
- Significant technical depth & experience with process technology, foundational IP, design automation, and competitive analysis / bench-marking methodologies that drive great insight (what, how & why) that results in key technology decision-making.
- Significant experience in market-target based PPA & EoU forecasting and analysis
- Excellent teaming & partnering skills with senior-level technical peers across Technology Development to jointly establish, influence and drive towards meaningful results that move the group-level needle. Exceptional organizational, planning & managerial skills that have been used to recruit, manage and grow diverse team of domain experts that have had significant influence & impact on key technology decisions and senior-level technologists / managers.
- Excellent communication and presentation skills developed from working many complex and challenging issues with engineering-level teams and senior-level management. Drives ad-hoc technical competitive analysis in partnership with various Intel groups to align on competitive data observations & conclusions based on data collected and analyzed, so that there's "one view" across the pertinent organizations.
PhD degree in Electrical Engineering, Computer Science, Physics, Materials Science or other related field of study.
A minimum of 15 years of relevant experience in process technology and silicon design.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.... US Experienced Hire JR0113618 Hillsboro
Meet Some of Intel's Employees
Martin S.SoC Design Engineer
Martin uses his communication skills and technical knowledge to perform deep-level debugs of the intellectual properties that come to Intel.
Back to top